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Power-Programmierung CD 2 (Tewi)(1994).iso
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ati.txt
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1994-01-18
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ATI Technologies Super VGA Chip Sets.
Board 18810 Dot ROM BIOS
Version Chip Clock Chip Label
V3 18800 no V3M
V4 18800-1 no V4M
V5 18800-1 yes V5M
V6 28800-2 VGA Wonder+
V7 28800-4 VGA Wonder XL
28800-5 VGA Graphics/Ultra (VGA chip)
? 38800-1 Mach 8. 8514/Ultra and Graphics/Ultra
(8514/A chip)
68800 Mach 32. Graphics Ultra Pro/+
Combined 8514/A and VGA chip.
Support chips:
ATI18810 Clock chip for 18800-1, 28800
ATI18811 Clock chip for 68800
ATI Prism Elite uses Trident 8800CS chips.
ATI VGA Wonder XL can use the Sierra HiColor RAMDAC.
Note that the base register for the ATI extended registers should be read from
the word at 0C000h:10h, as ATI reserves the right to change the base address.
However all current implementations use 1CEh.
1CEh index A0h (R/W): ATI Register 00h (28800+)
bit 0-3 Reserved
4 Enable 16bit ROM
5-7 Reserved
1CEh index A1h (R/W): ATI Register 01h (28800+)
bit 0-2 Reserved
3-4 Digital Monitor Detection
5-7 Reserved
1CEh index A2h (R/W): ATI Register 02h (28800+)
bit 0-7 Reserved
1CEh index A3h (R/W): ATI Register 03h (28800+)
bit 0-2 16bit ROM access
3 Cursor Start Address bit 17
4 Display start address bit 17
5-7 Reserved
1CEh index A4h (R/W): ATI Register 04h (28800+)
bit 0-3 ROM page 0
4-7 ROM page 1
1CEh index A5h (R/W): ATI Register 05h (28800+)
bit 0-3 ROM page 2
4-7 ROM page 3
1CEh index A6h (R/W): ATI Register 06h (28800+)
bit 0-6 Reserved
7 Forced read 3CCh
1CEh index A7h (R/W): ATI Register 07h (28800+)
bit 0 Enable True color mode
1,3 True Color DAC installed
2 Reserved
4-5 Forced pixel data to high
6 Skew display enable
7 Enable divide by 3 clock
1CEh index A8h (R/W): ATI Register 08h (28800-5 +)
bit 0-7 Reserved
1CEh index A9h (R/W): ATI Register 09h (28800-5 +)
bit 0-1 Vertical Line Counter bit 8-9
2-7 Reserved
1CEh index AAh (R/W): ATI Register 0Ah (28800-5 +)
bit 0-3 (R?) Chip Revision ID
4 Address/Data bus configuration
5-7 Reserved
1CEh index ABh (R/W): ATI Register 0Bh (28800+)
bit 0 Enable zero wait state support for video memory write
1 Enable zero wait state for BIOS read
2 Reserved
3 Select secondary display
4 (28800-6 +) Lock DAC write
5 (28800-6 +) Zero wait state enable
6 Restrict CPU access
7 Delay internal latching
1CEh index ACh (R/W): ATI Register 0Ch (28800-6 +)
bit 0 Enable Linear Addressing
1-5 Reserved
6 Enable 1024x768x16 color planar pass through internal palette
7 Reserved
1CEh index ADh (R/W): ATI Register 0Dh (28800-6 +)
bit 0 Extended Horizontal Total
1 Extended CRTC Start Blanking
2 (28800-6) Extended CRTC Horizontal Retrace
(Mach 32) Display Start Address bit 18.
3 Extended CRTC Registers Enable
4-7 Reserved
1CEh index AEh (R/W): ATI Register 0Eh
bit 0-1 (Mach 32) Write/Single bank bit 4-5
2-3 (Mach 32) Read bank bit 4-5
1CEh index AFh (R/W): ATI Register 0Fh
bit 0-7 Reserved
1CEh index B0h (R/W): ATI Register 10h
bit 0 Reserved
1 (188xx) Enable 256 color modes
(28800 +) Enable alt Video mem organization in text modes
2 (188xx) Enable 256 color modes
(28800 +) Extended Cursor Start Address
3 (188xx) Enable 8 CRT accesses for each CPU access
3-4 (28800-4 +) Video memory: 0=256k, 1=1M, 2=512K
4 (28800-2) Video memory: 0=256k, 1=512k
5 (28800 +) Enable 256 color modes if set
6 (28800 +) Display Start Address bit 16
6-7 (188xx) Display Start Address bit 16-17
1CEh index B1h (R/W): EGA Compatibility and Double Scanning Enable
bit 0 Force all I/O addresses to be EGA compatible if set
1 Force all registers to be EGA compatible if set
2 General purpose read/write
3-5 Double scanning/3 of 4 scanning enable
1: Enable double scanning in graphics mode
2: Enable 3 of 4 scanning in graphics mode
5: Enable double scanning in text mode
6: Enable 3 of 4 scanning in text mode
6 Divide vertical timing parameters by 2 if set
7 Reserved
1CEh index B2h (R/W): Memory Page Select
bit 0 (18800) Enable interlace if set
(18800-1) reserved
(28800 +) Read bank no bit 3
1-3 (18800-1) Write/Single bank no.
1-4 (28800 +) Write/Single bank no
(18800) Bank no. in 64 chunks
5 (18800) Enable internal DIP switch settings (EGA mode)
6 (18800) External clock select. If set 3C2h bits 2-3 selects from
(44.9 MHz, 50.175, <spare>, 36) rather than (50.175MHz,
56.644,<spare>, 44.9)
7 (18800) Reserved
5-7 (18800-1 +) Read bank no
1CEh index B3h (R/W): ATI Register 13h
bit 0 EEPROM data input
1 EEPROM clock source
2 Enable EEPROM interface
3 EEPROM chip select
4 (18800?) Enable PS/2 decoding
(18800-1) Disable memory beyond 256K
5 (28800 +) XOR with input status bit HSYNC to select 8 or 16 bit
video memory operation
6 (18800) Enable 1 CRT access to 1 CPU access
(18800-1 +) Enable 1024x768 16 color planar pixel mode
7 Enable double scanning for 200 line modes
Note: This register should not be modified on revision 1 chips.
1CEh index B4h (R/W): Emulation Control
bit 0 Enable CGA emulation if set
1 Enable Hercules emulation if set
2 Write Protect CR90-94,CR97
3 Write Protect all vertical timing registers if set
4 Write Protect cursor start and end if set
5 Write Protect CR80-86 and CR140-144
6 Write Protect CR0-7 instead of CR117
7 Override locking of CR117
1CEh index B5h (R/W): ATI Register 15h
bit 0 Select display enable as blanking signal
1 Invert blanking signal polarity
2 Enable display signal skew
3 Select Map 3 as programmable character generator
4 (18800-1 +) Enable 8 simultaneous fonts if set
Background is then always 0, and bit 4-7 of an
attribute selects the font.
5 Disable Cursor Blinking if set
6 Enable CGA Cursor Emulation if set
Adds 5 to the cursor start and end registers.
7 Select undivided input clock as pixel clock
1CEh index B6h (R/W): High Resolution Enable
bit 0 (28800-4 +) Set to enable display to cross the 256K limit
(512K in 256color modes).
1 Enable 640x400 Hercules emulation
2 Enable linear addressing in 256color modes
3 Select 4 color high res modes
4 Select 16 color high res modes
5 Enable vertical interrupts
6 (18800 - 28800-3) Enable linear addressing
(?) Select composite sync for output
7 Disable blanking screen blank in CGA and Hercules emulation
1CEh index B7h (R/W): ATI Register 17h
bit 0 16bit operation if set, 8bit if clear
1 PS/2 configuration
2 Video memory is DRAM if set, VRAM if clear
3 EEPROM data
4 Status of ROM address decode
5 Select I/O address at 3xxh or 2xxh
6-7 Reserved
1CEh index B8h (R/W): Write Protect and Clock Select
bit 0 Lock Palette registers in Attribute Controller if set
1 Lock Overscan register in Attribute Controller if set
2 Lock All VGA registers except CRTC start and end if set
3 Lock write to 3C2h if set
4 Lock horizontal sync polarity if set
5 Lock vertical sync polarity if set
6-7 Clock divider. Divide Video Clock by: 0: 1, 1: 2, 2: 3, 3: 4
1CEh index B9h (R/W): ATI Register 19h
bit 0 Clock select
1 (18800-1 +) Select input to clock chip. See index BEh bit 4
2-3 ROM address space.
0: 32k at C000h, 1: 28k at C000h, 2,3: 24k at C000h
4-5 Wait cycles for 16 bit ROM access:
0: 8 cycles, 1: 4 cycles, 2: 2 cycles, 3: none
6 (?) Set horizontal total = register value +2 (vs +5)
(?) I/O operations are 16bits if set, 8 if clear
7 Lock Line Compare register
1CEh index BAh (R/W): ATI Register 1Ah
bit 0-2 Delay chain timing compensation for TTL monitors and 16color RGB
simulation
3 Disable secondary Red output (for RGB monitors)
4 Enable EGA color simulation for RGB monitors
5 Enable monochrome grey scale circuit
6 reserved
7 Delay chain resolution compensation
1CEh index BBh (R/W): Input Status Register
bit 0-3 Monitor Type:
0: EGA
1: PS/2 Analog Monochrome
2: TTL Monochrome
3: PS/2 Color
4: RGB Color
5: MultiSync
7: PS/2 8514
8: Seiko 1430
9: NEC Multisync 2A
A: Crystalscan 860/Tatung 1439
B: NEC Multisync 3D
C: TVM 3M
D: NEC MultiSync XL
E: TVM 2A
F: TVM 3A
4 (188xx) General read/write bit
(28800 +) Bit 4 of the Monitor Type above
5 (188xx) Video memory is 512Kbytes if set, 256K else
6-7 Reserved
1CEh index BCh (R/W): ATI Register 1Ch
bit 0-7 reserved
1CEh index BDh (R/W): EGA Switch Settings
bit 0 Invert Composite Sync Polarity
2 (28800-5) 128K CPU address
4-7 EGA switch settings
1CEh index BEh (R/W): ATI Register E (not 18800)
bit 0 Unlock Vertical Display End register of the CRT Controller
1 Enable interlace mode
2 Select internal EGA DIP switch value
3 Dual bank mode if set, single else
4 (18800-1 without 18810 Clock Chip (V4)) External clock select.
If set 3C2h bits 2-3 selects from (44.9 MHz, 50.175, <spare>,
36) rather than (50.175MHz, 56.644, <spare>, 44.9)
4 (18800-1 with 18810 ClockChip, 28800 +) Clock Select
BEh bit 4: B9h bit 1: 3C2h bit 3: 3C2h bit 2: Frequency:
0 0 0 0 42.954 MHz
0 0 0 1 48.771
0 0 1 0 Ext 0 (16.657)
0 0 1 1 36.000
0 1 0 0 50.350
0 1 0 1 56.640
0 1 1 0 Ext 1 (28.322)
0 1 1 1 44.900
1 0 0 0 30.240
1 0 0 1 32.000
1 0 1 0 37.500
1 0 1 1 39.000
1 1 0 0 40.000
1 1 0 1 56.644
1 1 1 0 75.000
1 1 1 1 65.000
6 Enable 1024x768 16 color mode
7 Enable 1024x768 4 color mode
1CEh index BFh (R/W): Miscellaneous Register
bit 0 ??
6 ROM page address bit
7 Alternate memory organisation for graphics enable
3C0h (R/W): Palette index register
bit 4-5 Mode 67h Palette
Value Pixel=0 1 2 3
0 Black White Grey Bright White
1 Black Green Red Yellow
2 Black Cyan Red White
3 Black Cyan Magenta White
Note: The ATI chips handles the indexed registers slightly differently
from other VGA chips, as the index register must be written before
each read or write of the associated data register.
0AEEh W(R/W): (Mach 32 only)
bit 0-15 Lower bits of the address (in DWORDs) of the cursor map in video
memory. The upper bits are in 0EEEh. The cursor map is a 64x64 pixel
map with two bits per pixel.
0EEEh W(R/W): (Mach 32 only)
bit 0-14 Upper bits of the address of the cursor map. Low bits are in 0AEEh.
15 Set to enable the Hardware Cursor
12EEh W(R): (Mach 32 only)
bit 0 If set the VGA is enabled.
1-3 Bustype: 0: ISA, 1:EISA, 2:MCA, 3: MCA32, 4: Local Bus 386SX,
5: Local Bus 386, 6: Local Bus 486
4-6 Memory: 0: DRAM x4, 1: VRAM x4, 3: DRAM x16
9-11 DAC: 0: ATI 68830, 1: ATT20c491, 2: ATI 68875, 3: Bt476, 4: Bt481,
5: ATI 68860
12EE W(W): (Mach 32 only)
bit 0-15 Cursor X-position relative to the address in 2AEEh & 2EEEh
16EE W(W?): (Mach 32 only)
bit 0-15 Cursor Y-position relative to the address in 2AEEh & 2EEEh
1AEEh W(R/W): (Mach 32 only)
bit 0-7 Cursor Color FG ?
8-15 Cursor Color BG ?
1EEEh (R/W): (Mach 32 only)
bit 0-5 First horizontal pixel actually used within the 64x64 cursor map.
1EEFh (R/W): (Mach 32 only)
0-5 Number of lines shown in the cursor
2AEEh W(R/W): Cursor Position Low (Mach 32 only)
bit 0-15 Lower bits of the address of the cursor in DWORDs, calculated as:
[(Y position)*(bytes per scanline)+(X pos)*(bytes per pixel)]/4
The upper bits are in 2EEEh. This co-ordinates used in this
calculation must be modulo 8 and <= the actual position. The values
in 12EEh and 16EEh are added to give the actual cursor position.
2EEEh W(R/W): Cursor Position High (Mach 32 only)
bit 0-15 Upper bits of the address of the cursor. Lower bits are in 2AEEh.
36EEh (R/W): (Mach 32 only)
bit 2-3 Memory: 0: 512K, 1: 1MB, 2: 2MB, 3: 4MB
52EEh (R/W): (Mach 32 only)
bit 0-6 ROM address: 0: C000h, 1: C080h, 2: C100h ...
7
5EEEh W(R/W): (Mach 32 only)
bit 0-1 Aperture: 0: Disabled, 1: 1MB, 2: 4MB
8-15 Aperture address
9AEEh (R/W): (Mach 32 only)
bit 0 Set if busy ?
Bank Switching
Bank switching can use either one single bank register or two
separate read and write bank registers (18800-2 and 28800 Only).
Banks map to 64k boundaries.
Reserved locations:
$C000:$10 2 bytes ATI Register (usually $1CE).
$C000:$31 9 bytes '761295520' ID's ATI product
$C000:$40 2 bytes '31' ID's ATI Super VGA
'32' = ATI EGA Wonder 800+
'22' = ATI EGA Wonder
?+'3' = ATI Basic-16
$C000:$42 1 byte Bit 0 Set for 16-bit boards
1 Mouseport present if set
2 Non-interlace if set
3 Microchannel if set, PC/AT else
4 Use clock chip if set
7 Use C000:0000 to D000:FFFF with 16 bit ROM
if set
$C000:$43 1 byte Gate revision.
'1' = 18800 (V3),
'2' = 18800-1 (V4/V5),
'3' = 28800-2 (V6).
'4' = 28800-4 VGA Wonder+
'5' = 28800-5 VGA Wonder XL
'a' = 68800 Mach-32
Note: Types '6' and 'c' have been reported
$C000:$44 1 byte Bit 0 If clear the board can support 70Hz
non-interlaced refresh
1 If set the board supports Korean characters
in VGA mode
2 If set the board uses 45MHz memory clock
3 If set the board supports zero wait states.
4 If set the board uses paged ROMs.
6 If clear there is 8514/A hardware on board
(Graphics Ultra)
7 If set there is a 32K color DAC on board.
$C000:$4C 1 byte Major Bios version
$C000:$4D 1 byte Minor Bios version
ID ATI Super VGA Chip Set
if (getbios($31,9)='761295520') and (getbios($40,2)='31') then
begin
{ATI_Super_VGA}
case mem[$C000:$43] of
$31: ATI 18800;
$32: ATI 18800-1;
$33: ATI 28800-2;
$34: ATI 28800-4;
$35: ATI 28800-5;
$61: ATI Graphics Ultra Pro;
else unknown_ATI
end
end;
Video Modes:
23h T 132 25 16 (8x14)
27h T 132 25 2 (8x14)
33h T 132 44 16 (8x8)
37h T 132 44 2 (8x8)
51h G 640 480 16 PL4 ATI EGA Wonder only
52h G 752 410 16 PL4 ATI EGA Wonder only
53h G 800 560 16 PL4
54h G 800 600 16 PL4
55h G 1024 768 16 PL4 (V4 or later)
58h T 80 33 16 (8x8)
5Bh T 80 30 (8x16)
61h G 640 400 256 P8
62h G 640 480 256 P8
63h G 800 600 256 P8
64h G 1024 768 256 P8 V6 (VGA Wonder +) or later
65h G 1024 768 16 P4 **** See note
67h G 1024 768 4 PL2E **** See note
6Ah G 800 600 16 PL4 Undocumented ??
72h G 640 480 32k P15 V7 (XL) only
73h G 800 600 32k P15 V7 (XL) only
75h G 640 480 16m P24 XL24 only
Note: ATI Prism Elite uses a Trident chip and Trident mode numbers.
ATI enhanced Graphics modes do NOT support INT 10h with AH=
01h..0Eh or 11h or 13h.
Mode 65h 1024x768 16 color
4 bits per pixel packed mode
Even pixel is in bits 0-3 of the byte, odd in bits 4-7.
Mode 67h 1024x768 4 color
2 bits per pixel planar mode
Even pixels are in plane 2&3, odd pixels in plane 0&1.
BIOS extensions:
----------1012--BH55-------------------------
INT 10 - VIDEO - ALTERNATE FUNC SELECT (ATI,Tatung,Taxan) - ENHANCED FEATURES
AH = 12h
BH = 55h
BL = subfunction
00h disabled enhanced features
01h enable enhanced features
02h get status
Return: AL = status flags
bit 3 set if enhanced features enabled
bits 7-5 monitor type
000 PS/2 mono
001 PS/2 color
010 multi-sync
011 Taxan 650 25kHz
100 RGB
101 mono
110 EGA
111 Compaq internal
03h disable register trapping (CGA emulation)
04h enable register trapping
05h program mode described by table at ES:BP
06h get mode table
AL = video mode
BP = FFFFh (Known illegal value).
SI = 0000h (Known illegal value).
Return: ES:BP -> table suitable for mode AL (and subfnc BL=05h)
BP = FFFFh on error
Format of ATI VGA Wonder video mode table:
Offset Size Description
00h BYTE number of columns
01h BYTE maximum row (number of rows - 1)
02h BYTE scan lines per row
03h WORD video buffer size in bytes
05h 4 BYTEs values for Sequencer registers 1-4
09h BYTE value for Miscellaneous Output register
0Ah 25 BYTEs values for CRTC registers 00h-18h
00h horizontal total size (chars)
01h horizontal displayed (chars)
02h horizontal sync position (chars)
03h horizontal sync width (chars)
04h vertical total size (char rows)
05h vertical total adjust (scan lines)
06h vertical displayed (char rows)
07h vertical sync position (char rows)
08h interlace mode
09h max scan line in row
0Ah cursor start scan line
0Bh cursor end scan line
0Ch screen memory start (high)
0Dh screen memory start (low)
0Eh cursor address (high)
0Fh cursor address (low)
10h light pen (high)
11h light pen (low)
23h 20 BYTEs default palette (values for Attribute Controller regs
00h-13h)
37h 9 BYTEs values for Graphics Controller registers 00h-08h
